The present invention relates to power supply circuits. More particularly, the present invention relates to a composite loop compensation method and circuit, such as may be used with low drop-out regulators.
The increasing demand for higher performance power supply circuits has resulted in the continued development of voltage regulator devices. Many low voltage applications are now requiring the use of low drop-out (LDO) regulators, such as for use in cellular phones, pagers, laptops, camera recorders and other mobile battery operated devices as power supply circuits. These portable electronics applications typically require low voltage and quiescent current flow to facilitate increased battery efficiency and longevity. The alternative to low drop-out regulators are switching regulators which operate as dcxe2x80x94dc converters. Switching regulators, though similar in function, are not preferred to low drop-out regulators in many applications because switching regulators are inherently more complex and costly, i.e., switching regulators can have higher cost, as well as increased complexity and output noise than low drop-out regulators.
Low drop-out regulators generally provide a well-specified and stable dc voltage whose input to output voltage difference is low. Low drop-out regulators are generally configured for providing the power requirements, i.e., the voltage and current supply, for any downstream portion of the electrical circuit. Low drop-out regulators typically have an error amplifier in series with a pass device, e.g., a power transistor, which is connected in series between the input and the output terminals of the low drop-out regulator. The error amplifier is configured to drive the pass device, which can then drive an output load.
To provide for a more robust low drop-out regulator, a large load capacitor is provided at the output of the low drop-out regulator. However, using large capacitors at the output of the low drop-out regulator requires a significant amount of board area, as well as increases manufacturing costs. Further, larger capacitors can tend to slow the response time down of the low drop-out regulator.
For example, with reference to FIG. 1, a prior art circuit 100 implementing a low drop-out regulator is illustrated. Circuit 100 includes a low drop-out regulator 102 coupled to a downstream circuit device, e.g., a digital signal processor (DSP) 104. At the input of low drop-out regulator 102 is a supply voltage VIN, such as a low voltage battery supply of 3.3 volts or less, and an input capacitor C1. At an output VOUT of low drop-out regulator 102, a regulated output of, for example, 2.5 volts can be provided to the downstream circuit elements and devices. In addition, a large load capacitor C2 is provided at output VOUT of low drop-out regulator 102. In addition to enabling low drop-out regulator 102 to be more robust, load capacitor C2 can provide compensation to low drop-out regulator 102 to enable low drop-out regulator 102 to work properly. This compensation of low drop-out regulator 102 can be highly sensitive to the configuration of capacitor C2.
Downstream elements and devices are coupled to output VOUT of low drop-out regulator 102 through various circuit traces and wiring connections. Capacitor C2 also serves as an input capacitor for DSP 104. As the input capacitor, designers of applications for DSP 104 typically require capacitor C2 to comprise between 10 xcexcF and 100 xcexcF of capacitance to facilitate noise reduction in DSP 104. Thus, in most applications, capacitor C2 is based on the requirement of the downstream circuit and components, such as DSP 104, rather than the compensation requirements of low drop-out regulator 102. As a result, the design of low drop-out regulator 102, including the compensation requirements, is generally limited by the bypass requirements of the downstream circuit devices and elements.
Input capacitance devices, such as capacitor of DSP 104, also include an equivalent series resistance (ESR) that must be accounted for in the design of low drop-out regulator 102. Further, for downstream circuits with high transient requirements, the total capacitance is ideally configured to tailor the overshoot and undershoot of low drop-out regulator 102. In many instances, the design of a compensation circuit for low drop-out regulator 102 can involve substantial guesswork as to the range of total capacitance, and the ESR of such capacitance, expected to be included within the downstream circuit. Thus, prior art low drop-out regulators, and their required compensation, are generally configured for a particular range of ESR and total capacitance for downstream circuit devices. As a result, circuit designers must pick and choose a particular low drop-out regulator configured for a given ESR and total capacitance of a downstream circuit application.
In addition to the need to identify the capacitance requirements of the downstream circuit in designing the compensation circuit for low drop-out regulator 102, it is also necessary to address poles created within a low drop-out regulator. Whenever a pole is introduced in the frequency response, the gain of low drop-out regulator decreases by more than 20 dB/decade. Poles can be generated or caused by various sources, and occur at various locations within the frequency response of a low drop-out regulator or other output stage circuit. For example, one pole comprising a dominant pole often occurs at a very low frequency, such as 10 Hz; another pole can often occur from an internal loop; and yet another pole can be caused by various parasitics and the gm in the low drop-out regulator, e.g., the additional pole can be caused in some topologies by the interaction of the low gm of the error amplifier with the gate capacitance of the typically large common source pass device. With reference to FIG. 2, three such poles are illustrated. However, the frequency responses of low drop-out regulators can include fewer or additional poles to the three types discussed above.
While the first pole is typically not problematic for low drop-out regulator 102, and the third pole can be addressed through use of a pole-zero compensation techniques, such as is disclosed in U.S. patent application Ser. No. 10/107,270, entitled xe2x80x9cOutput Stage Compensation Circuitxe2x80x9d, filed on Mar. 25, 2002, and having common inventor and a common assignee as this application, the second pole is more difficult to compensate in low drop-out regulators applications having a large output capacitor C2 with a high ESR. One approach to address the second pole P(2) is to limit the bandwidth of low drop-out regulator 102 by pulling back the dominant first pole P(1) to a lower frequency, thus slowing down low drop-out regulator 102, which results in stable operation at lower currents. However, such bandwidth limitations are problematic for higher current applications, and thus are not favorable.
In addition, prior art low drop-out regulators are required to use smaller sized pass devices with higher resistance values since large sized pass devices are more difficult to control at lower currents. Thus, smaller pass devices having a resistance of 500 mxcexa9 or more require additional supply voltage from battery supplies to provide a desired output voltage.
Accordingly, a need exists for an improved compensation method and circuit for low drop-out regulators that can overcome the various problems of the prior art.
The method and circuit according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a composite loop compensation circuit and method for a low drop-out regulator configured to facilitate stable operation while providing output voltage and current to downstream circuit devices is provided.
In accordance with an exemplary embodiment, an exemplary low drop-out regulator comprises an error amplifier, a pass device, and a composite loop compensation circuit. The error amplifier is configured to provide an output current that can be configured to drive a control terminal of the pass device, and includes a capacitance device coupled in a feedback arrangement between the output of the error amplifier and the inverting input terminal of the error amplifier. An active resistor component is coupled between an output terminal of the pass device and the inverting input terminal of the error amplifier to provide a composite feedback loop in the low drop-out regulator. The active resistor component and the capacitance device are configured to provide a dominant first pole of the low drop-out regulator.
In accordance with an exemplary embodiment, an exemplary composite loop compensation circuit comprises one or more segmented sense devices configured to drive one or more current sources. Each segmented sense device is configured to sense a suitable range of output load current, i.e., the current from the output terminal of the pass device, and is coupled to a biasing component which controls the biasing of the active resistor. The biasing component is configured with one or more switches coupled to the outputs of one or more segmented current sense devices. Each segmented current sense device along with the biasing component is configured to facilitate compensation for a suitable range of output load current. Composite loop compensation circuit is configured to adjust the dominant first pole of the composite feedback loop based on the biasing current through the active resistor component. As a result, the low drop-out regulator can include a very large pass device for addressing high currents and can remain stable for extremely low currents.
In accordance with another exemplary embodiment, the biasing component is configured to bias the active resistor component through biasing of the control terminal of the active resistor component. In accordance with an exemplary embodiment, the active resistor device comprises a PMOS device and the biasing component comprises a diode-connected PMOS device.